Digital sum variation computation method and system

ABSTRACT

A digital sum variation (DSV) computation method and system is proposed, which is capable of determining the DSV value of a bit stream of channel-bit symbols to thereby find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols. This DSV computation method and system is characterized in the use of a Zero Digital Sum Variation (ZDSV) principle to determine the DSV. This DSV computation method and system can find the optimal merge-bit symbol for insertion between each succeeding pair of the channel-bit symbols in a more cost-effective manner with the need for a reduced amount of memory and utilizes a lookup table requiring a reduced amount of memory space for storage so that memory space can be reduced as compared to the prior art. This DSV computation method and system is therefore more advantageous to use than the prior art.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation application of, and claims thepriority benefit of, U.S. application Ser. No 10/370,261 filed on Feb.19, 2003, now U.S. Pat. No. 6,853,684 which is a continuationapplication of U.S. application Ser. No. 09/494,176 filed on Jan. 31,2000, now U.S. Pat. No. 6,542,452 issued on Apr. 1, 2003, which claimsthe priority benefit of Taiwan application serial No 88117002, filedOct. 2, 1999.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to digital technology, and more particularly, toa digital sum variation (DSV) computation method and system which iscapable of determining the DSV value of a bit stream of channel-bitsymbols to thereby find the optimal merge-bit symbol for insertionbetween each succeeding pair of the channel-bit symbols.

2. Description of Related Art

In a CD (compact disc) system, analog audio signals are processedthrough sampling and analog-to-digital conversion into a stream ofdigital data. Typically, the digital data are formatted into 16-bitwords, with each word consisting of two bytes. By convention, each byteof the digital data is referred to as a symbol. These digital data arethen written onto a CD. There exist, however, some problems when readingthese digital data from the CD if these data are directly written ontothe CD without further processing.

Conventionally, these digital data should be further processed throughthe what is known as an eight-to-fourteen modulation (EFM) to converteach 8-bit symbol into a 14-bit data length called channel bits (eachset of channel bits is hereinafter referred to as a channel-bit symbol.The EFM process is achieved through the use of a lookup table. Thelength of each channel-bit symbol should be compliant with the specifiedrun length of the CD driver between 3 bits and 11 bit.

During a write operation, it is possible that the current channel-bitsymbol and the next one are not compliant with the specified run length.One solution to this problem is to insert 3 bit, called merge bits,between each succeeding pair of channel-bit symbols, so as to ensurethat all the data written onto the CD are absolutely compliant with therun length.

There are four merge-bit symbols (000), (001), (010), and (100) whichcan be selected for insertion between each succeeding pair ofchannel-bit symbols; through computation, the optimal merge-bit symbolcan be found for the insertion.

During write operation, a pit is formed in the CD surface for eachchange of binary value. During read operation, the CD driver can producea what is known as a Non-Return-to-Zero-and-Invert (NRZI) signal basedon the pattern of the pits on the CD.

FIG. 1 is a schematic diagram used to depict the generation of an NRZIsignal and a bit stream from a pattern of pits on a CD. During the read,when a pit is encountered, it represents a logic change from 0 to 1 orfrom 1 to 0. The starting logic voltage state for the NRZI signal can beeither LOW or HIGH. In the example of FIG. 1, the NRZI signal waveform(I) has a LOW starting logic voltage state, whereas the NRZI signalwaveform (II) has a HIGH starting logic voltage state. In either case,the CD driver can produce a bit stream of channel-bit symbols (efm₁,efm₂, efm₃) and a number of merge-bit symbols (m₁, m₂, m₃) each beinginserted between one succeeding pair of the channel-bit symbols. Themerge-bit symbols (m₁, m₂, m₃) can be removed later to obtain thechannel-bit symbols (efm₁, efm₂, efm₃) which are then processed throughreverse EFM to recover the original 8-bit symbols (SYM₁, SYM₂, SYM₃).

In the case of the NRZI signal waveform (I), whose starting logicvoltage state is LOW, its digital sum variation (DSV), here representedby DSV₁, can be computed as follows: since efm₁=(01001000100000), theDSV₁ value at t₀ is 0; subsequently, since the first bit 0 is at the LOWstate, the DSV₁ value becomes −1; subsequently, since the next threebits 100 are at the HIGH state, the DSV₁ value becomes −1+3=+2;subsequently, since the next four bits 1000 are at the LOW state, theDSV₁ value becomes +2 −4=−2; and subsequently, since the next six bits1000000 are at the HIGH state, the DSV₁ value becomes −2+6=+4.

Subsequently at t₂ (i.e., at the end of m₂), the DSV₁ value becomes +5;at t₃ (i.e., at the end of efm₂), the DSV₁ value becomes −3; at t₄(i.e., at the end of m₃), the DSV₁ value becomes −2; at t₅ (i.e., at theend of efm₃), the DSV₁ value becomes 0. The DSV for the NRZI signalwaveform (II), here denoted by DSV₂, is simply the negative of the DSV₁value, i.e., DSV₂=−DSV₁ at any time point.

What is described above is how the pattern of pits on a CD can beconverted into a stream of bit data during read operation. The encodingof the original digital data through EFM with insertion of merge bitsbefore being written onto the CD is rather complex in procedure. TheU.S. Pat. No. 5,375,249 entitled “EIGHT-TO-FOURTEEN-MODULATION CIRCUITFOR A DIGITAL AUDIO DISC SYSTEM” issued on Dec. 20, 1994 discloses amethod for finding the optimal merge-bit symbol through the use of DSV.This patented method is briefly depicted in the following with referenceto FIG. 2.

Referring to FIG. 2, after efm₁ and efm₂ are obtained, four bit streamsare obtained by inserting each of the following four merge-bit symbols:(000), (001), (010), and (100), between efm₁ and efm₂. After this, therespective DSV values for these four bit streams are computed, which arerespectively denoted by DSV₁, DSV₂, DSV₃, and DSV₄.

Next, whether the length of the merge bits inserted between efm₁ andefm₂ exceeds the specified run length is checked; if the length isexceeded, these merge bits are inhibited from insertion between efm₁ andefm₂. To do this, a check is conducted for each of the four bit streamsas to whether the number of consecutive 0s between the last 1 and thenext 1 in efm₁ exceeds the run length, and whether the number ofconsecutive 0s between the first 1 and the preceding 1 in efm₂ exceedsthe run length.

In the example of FIG. 2, efm₁=(01001000100000), efm₂=(00100100000000),and efm₃=(01000001000000). Then, the insertion of each of the fourmerge-bit symbols: m₁=(000), m₂=(001), m₃=(010), and m₄=(100), betweenefm₁ and efm₂ results in four bit streams, with DSV₁=+15, DSV₂=−3,DSV₃=−5, and DSV₄=−7, where DSV₁ is the DSV of the bit stream (efm₁, m₁,efm₂); DSV₂ is the DSV of the bit stream (efm₁, m₂, efm₂); DSV₃ is theDSV of the bit stream (efm₁, m₃, efm₂); and DSV₄ is the DSV of the bitstream (efm₁, m₄, efm₂). Among these DSV values, DSV₂=−3 is closest to0, and the associated merge-bit symbol m₂=(001) is therefore chosen forinsertion between efm₁ and efm₂.

In a similar manner, for efm₂ and efm₃, the DSV value of −8 can beobtained for the bit stream (efm₂, m₁, efm₃). The bit stream (efm₂, m₂,efm₃) is not compliant with the run length and is therefore disregardedthe DSV value for the bit stream (efm₂, efm₃, efm₃) is 0, and the DSVvalue for the bit stream (efm₂, m₄, efm₃) is 2. Among these DSV values,DSV=0 is closest to 0, and the associated merge-bit symbol m₃=(010) istherefore chosen for insertion between efm₂ and efm₃. An NRZI signal canbe then obtained based on the resulting bit stream (efm₂, m₃, efm₃).

One drawback to the foregoing method, however, is that a large amount ofmemory space is required to implement the DSV-based algorithm forfinding the optimal merge-bit symbol for insertion between eachsucceeding pair of the 14-bit channel-bit symbols. This is because thatthe method requires the storage of a lookup table used in the EFMprocess and the binary data of each 14-bit channel-bit symbols, whichare quite memory-consuming. Moreover, the process for finding theoptimal merge-bit symbol is quite complex in procedure, and requires alengthy program to implement.

SUMMARY OF THE INVENTION

It is therefore an objective of this invention to provide a DSVcomputation method and system, which can find the optimal merge-bitsymbol based on DSV in a more cost-effective manner with the need of areduced amount of memory.

It is another objective of this invention to provide a DSV computationmethod and system, which utilizes a lookup table requiring a reducedamount of memory space for storage so that memory space can be reducedcompared to the prior art.

In accordance with the foregoing and other objectives, the inventionproposes a new DSV computation method and system. The DSV computationmethod and system of the invention is capable of determining the DSVvalue of a bit stream of channel-bit symbols to thereby find the optimalmerge-bit symbol for insertion between each succeeding pair of thechannel-bit symbols.

In terms of system, the invention comprises the following constituentparts: (a) an EFM processing unit for converting each original binarysymbol into its corresponding channel-bit symbol; (b) a PDSV processingunit for processing each original binary symbol to obtain itschannel-bit symbol PDSV; (c) a channel-bit symbol inhibit circuit,receiving the output channel-bit symbol from the EFM processing unit andunder control of a m_(n—)SEL signal, for determining which one of themerge-bit symbols is invalid for compliance with a specified run length;(d) an ODD checking circuit, receiving the output channel-bit symbolfrom the EFM processing unit and under control of a m_(n—)SEL signal,for determining, based on a previous start-to-channel-bit ODD value, anumber of start-to-channel-bit ODD values for the merge-bit symbols,respectively; (e) a DSV computation and search circuit, coupled to thePDSV processing unit and the ODD checking circuit, for computing for therespective DSV values corresponding to the merge-bit symbols based onthe current start-to-channel-bit ODD, the PDSV, the previousstart-to-channel-bit ODD, the previous ZDSV, which DSV computation andsearch circuit is under control of the channel-bit symbol inhibitcircuit to eliminate any of the DSV values corresponding to an invalidmerge-bit symbol determined by the channel-bit symbol inhibit circuit,the DSV computation and search circuit outputting an index signalindicative of the selected merge-bit symbol using as the optimalmerge-bit symbol for insertion between the current channel-bit symboland the previous channel-bit symbol; (f) a third buffer, coupled to theDSV computation and search circuit, for temporary storage of theprevious start-to-channel-bit ODD; and (g) a second buffer, coupled tothe DSV computation and search circuit, for temporary storage of theprevious ZDSV.

In terms of method, the invention comprises the following steps: (1)fetching the current channel-bit symbol; and then, based on the startinglogic voltage state of an NRZI signal, determining the PDSV and ODD ofthe current channel-bit symbol; (2) assigning the current channel-bitsymbol PDSV as the previous channel-bit symbol ZDSV, and assigning thecurrent channel-bit symbol ODD as the previous channel-bit symbol ODD;(3) fetching the next channel-bit symbol; and then, based on thestarting logic voltage state of the NRZI signal, determining the PDSVand ODD of this channel-bit symbol; (4) from four merge-bit symbolsincluding a first merge-bit symbol, a second merge-bit symbol, a thirdmerge-bit symbol, and a fourth merge-bit symbol, selecting the firstmerge-bit symbol; and then determining the first merge-bit symbol PDSVand ODD; and then performing an XOR logic operation on the previouschannel-bit symbol ODD and the first merge-bit symbol ODD to therebyobtain a start-to-the-first-merge-bit ODD; and then determining the ZDSVvalue for the first merge-bit symbol based on the previous channel-bitsymbol ZDSV and the first PDSV; and then, in the case of the startinglogic voltage state of the NRZI signal being LOW, determining the resultof the first ZDSV plus the start-to-next-channel-bit ODD to therebyobtain a first DSV corresponding to the first merge-bit symbol; andwhile in the case of the starting logic voltage state of the NRZI signalbeing HIGH, determining the result of the first ZDSV minus thestart-to-next-channel-bit ODD to thereby obtain a first DSVcorresponding to the first merge-bit symbol; and then checking whetherthe resulting bit stream from the first merge-bit symbol exceeds aspecified run length; if YES, eliminating the first DSV; (5) selectingthe second merge-bit symbol; and then determining the second merge-bitsymbol PDSV and ODD; and then performing an XOR logic operation on theprevious channel-bit symbol ODD and the second merge-bit symbol ODD tothereby obtain a start-to-the-second-merge-bit ODD; and then determiningthe ZDSV value for the second merge-bit symbol based on the previouschannel-bit symbol ZDSV and the second PDSV; and then, in the case ofthe starting logic voltage state of the NRZI signal being LOW,determining the result of the second ZDSV plus thestart-to-next-channel-bit ODD to thereby obtain a second DSVcorresponding to the second merge-bit symbol; and while in the case ofthe starting logic voltage state of the NRZI signal being HIGH,determining the result of the second ZDSV minus thestart-to-next-channel-bit ODD to thereby obtain a second DSVcorresponding to the second merge-bit symbol; and then checking whetherthe resulting bit stream from the second merge-bit symbol exceeds aspecified run length; if YES, eliminating the second DSV; (6) selectingthe third merge-bit symbol; and then determining the third merge-bitsymbol PDSV and ODD; and then performing an XOR logic operation on theprevious channel-bit symbol ODD and the third merge-bit symbol ODD tothereby obtain a start-to-the-third-merge-bit ODD; and then determiningthe ZDSV value for the third merge-bit symbol based on the previouschannel-bit symbol ZDSV and the third PDSV; and then, in the case of thestarting logic voltage state of the NRZI signal being LOW, determiningthe result of the third ZDSV plus the start-to-next-channel-bit ODD tothereby obtain a third DSV corresponding to the third merge-bit symbol;and while in the case of the starting logic voltage state of the NRZIsignal being HIGH, determining the result of the third ZDSV minus thestart-to-next-channel-bit ODD to thereby obtain a third DSVcorresponding to the third merge-bit symbol; and then checking whetherthe resulting bit stream from the third merge-bit symbol exceeds aspecified run length; if YES, eliminating the third DSV; (7) selectingthe fourth merge-bit symbol; and then determining the fourth merge-bitsymbol PDSV and ODD; and then performing an XOR logic operation on theprevious channel-bit symbol ODD and the fourth merge-bit symbol ODD tothereby obtain a start-to-the-fourth-merge-bit ODD; and then determiningthe ZDSV value for the fourth merge-bit symbol based on the previouschannel-bit symbol ZDSV and the fourth PDSV; and then, in the case ofthe starting logic voltage state of the NRZI signal being LOW,determining the result of the fourth ZDSV plus thestart-to-next-channel-bit ODD to thereby obtain a fourth DSVcorresponding to the fourth merge-bit symbol; and while in the case ofthe starting logic voltage state of the NRZI signal being HIGH,determining the result of the fourth ZDSV minus thestart-to-next-channel-bit ODD to thereby obtain a fourth DSVcorresponding to the fourth merge-bit symbol; and then checking whetherthe resulting bit stream from the fourth merge-bit symbol exceeds aspecified run length; if YES, eliminating the fourth DSV; (8) findingwhich one of the non-eliminated DSV values has the minimum absolutevalue; (9) if the first DSV has the minimum absolute value, thenassigning the current channel-bit symbol as the previous channel-bitsymbol, the first ZDSV as the previous channel-bit symbol ZDSV, and thecurrent start-to-channel-bit ODD as the previous channel-bit symbol ODD;then jumping to the step (3); (10) if the second DSV has the minimumabsolute value, then assigning the current channel-bit symbol as theprevious channel-bit symbol, the second ZDSV as the previous channel-bitsymbol ZDSV, and the current start-to-channel-bit ODD as the previouschannel-bit symbol ODD; then jumping to the step (3); (11) if the thirdDSV has the minimum absolute value, then assigning the currentchannel-bit symbol as the previous channel-bit symbol, the third ZDSV asthe previous channel-bit symbol ZDSV, and the currentstart-to-channel-bit ODD as the previous channel-bit symbol ODD; thenjumping to the step (3); and (12) if the fourth DSV has the minimumabsolute value, then assigning the current channel-bit symbol as theprevious channel-bit symbol, the fourth ZDSV as the previous channel-bitsymbol ZDSV, and the current start-to-channel-bit ODD as the previouschannel-bit symbol ODD; then jumping to the step (3).

BRIEF DESCRIPTION OF DRAWINGS

The invention can be more fully understood by reading the followingdetailed description of the preferred embodiments, with reference madeto the accompanying drawings, wherein:

FIG. 1 (PRIOR ART) is a schematic diagram used to depict the generationof an NRZI signal and a bit stream from a pattern of pits on a CD;

FIG. 2 (PRIOR ART) is a schematic diagram used to depict how aconventional method is used to obtain the optimal merge-bit symbol forinsertion between each succeeding pair of channel-bit symbols;

FIG. 3 a shows a comparison between DSV and ZDSV in the case of thestarting logic voltage state being LOW and the total of 1s being an oddnumber;

FIG. 3 b shows a comparison between DSV and ZDSV in the case of thestarting logic voltage state being LOW and the total of 1s being an evennumber;

FIG. 4 is a schematic diagram used to depict the algorithm used tocompute for ZDSV;

FIG. 5 is a schematic diagram used to show a comparison between DSV andZDSV in the case of the starting logic voltage state of the NRZI signalbeing HIGH and the total of 1s being an odd number;

FIG. 6 is a schematic block diagram showing the system architecture ofthe DSV computation method and system according to the invention;

FIG. 7 is a schematic diagram showing the inside circuit architecture ofthe ODD checking circuit used in the DSV computation system of theinvention shown in FIG. 6;

FIG. 8 is a schematic diagram showing the inside architecture of the DSVcomputation circuit used in the DSV computation system of the inventionshown in FIG. 6; and

FIG. 9 is a schematic diagram used to depict how to compute for ZDSV ina DVD system.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In the following detailed description of the invention, the algorithmutilized by the invention will be first introduced, following theimplementation of the algorithm.

Algorithm Utilized by the Invention

The invention utilizes a new concept called Zero Digital Sum Variation(ZDSV). Based on the ZDSV principle, each 0 in the NRZI signal isregarded as a “−1” if the 0 is at the LOW state and as a “+1” if the 0is at the HIGH state.

FIG. 3A shows a comparison between DSV and ZDSV when the starting logicvoltage state of the NRZI signal is LOW and the total number of 1s is anodd number. As shown, at the start, the ZDSV value is 0; subsequently atthe appearance of the first 0, since this 0 is at the LOW state, theZDSV value becomes −1; since the next three bits 100 are at the HIGHstate and include two 0s, the ZDSV value becomes −1+2=+1; subsequently,since the next four bits 1000 are at the LOW state and include three 0s,the ZDSV value becomes −1+2−3=−2; and subsequently, the next six bit100000 are at the HIGH state and include five 0s, the ZDSV value becomes−1+2−3+5=+3 at t₁. (i.e., at the end of efm₁).

Subsequently, at t₂, the ZDSV value becomes +1 for the bit stream (efm₁,m₂); at t₃, the ZDSV value becomes −3 for the bit stream (efm₁, m₂,efm₂); at t₄, the ZDSV value becomes −3 for the bit stream (efm₁, m₂,efm₂, m₃); and at t₅, the ZDSV value becomes 3 for the bit stream (efm₁,m₂, efm₂, m₃, efm₃).

By contrast, based on the conventional DSV method, the DSV value variesin such a manner that, at t₂, the DSV value is +4; at t₃, the DSV valuebecomes −3; at t₄, the DSV value becomes −2; and at t₅, the DSV valuebecomes +4.

FIG. 3B shows a comparison between DSV and ZDSV when the starting logicvoltage state is LOW and the total number of 1s is an even number.

As shown, at t₁, the ZDSV value is +3; at t₂, the ZDSV value becomes +6;at t₃, the ZDSV value becomes +10; at t₄, the ZDSV value is still +10;and at t₅, the ZDSV value becomes +4.

By contrast, based on the conventional DSV method, the DSV value variesin such a manner that, at t₁, the DSV value is +4; at t₂, the DSV valuebecomes +7; at t₃, the DSV value becomes +11; at t₄, the DSV valuebecomes +10; and at t₅, the DSV value becomes +4.

From the foregoing examples of FIGS. 3A and 3B, it can be learned thatwhen the total number of 1s is an odd number, the NRZI signal varies involtage state for an odd-number of times, and the difference between theZDSV value and the DSV value is 1 (i.e., DSV=ZDSV+1); whereas when thetotal number of 1s is an even number, the NRZI signal varies in voltagestate for an even-number of times, and the difference between the ZDSVvalue and the DSV value is 0 (i.e., ZDSV=DSV).

In the forgoing case, the computation for ZDSV and the conversion ofZDSV into DSV are disclosed in the following. The algorithm involves theuse of the following variables: GZ_(n), ZDSV, PDSV(SEGMENT),ZDSV(SEGMENT), and ODD(SEGMENT), which are introduced in the following.

GZ_(n).

Assume that, in a bit stream, each series of consecutive 0s arecollected as a group, with 1 serving as the separator between eachneighboring pair of groups. Furthermore, assume that GZ_(n) representsthe total number of 0s in the (n)th group. In the example of FIG. 3A,starting at t₀, it can be easily seen that GZ₁=1, GZ₂=2, GZ₃=3, GZ₄=5,and so forth.

ZDSV

When the starting logic voltage state of the NRZI signal is LOW, it isapparent that the first 0 group is minus. It can be deduced that:

${ZDSV} = {\sum\limits_{x = 1}^{n}{{GZ}_{x} \cdot \left( {- 1} \right)^{x}}}$In the example of FIG. 3A, at t₅, a total of ten 0 groups are collected,and therefore,

$\begin{matrix}{{ZDSV} = {{{GZ}_{1} \cdot \left( {- 1} \right)} + {{GZ}_{2} \cdot \left( {+ 1} \right)} + {{GZ}_{3} \cdot \left( {- 1} \right)} + {{GZ}_{4} \cdot \left( {+ 1} \right)} +}} \\{{{GZ}_{5} \cdot \left( {- 1} \right)} + {{GZ}_{6} \cdot \left( {+ 1} \right)} + {{GZ}_{7} \cdot \left( {- 1} \right)} + {{GZ}_{8} \cdot \left( {+ 1} \right)} +} \\{{{GZ}_{9} \cdot \left( {- 1} \right)} + {{GZ}_{10} \cdot \left( {+ 1} \right)}} \\{= {\left( {- 1} \right) + (2) + \left( {- 3} \right) + (5) + \left( {- 2} \right) + (4) + \left( {- 9} \right) + (2) + \left( {- 3} \right) + (8)}} \\{= 3}\end{matrix}$PDSV(SEGMENT)

PDSV(SEGMENT) refers to Partial ZDSV, which represents the ZDSV value ofa particular segment in the total bit stream, where the segment can beone of the 14-bit channel-bit symbols efm₁, efm₂, efm₃, or one of the3-bit merge-bit symbols m₂, m₃ inserted among efm₁, efm₂, efm₃. By PDSV,the first group starts at the beginning of a channel-bit symbol or amerge-bit symbol. It can be formulated as follows:

${PDSV} = {\sum\limits_{x = 1}^{n}{{GZ}_{x} \cdot \left( {- 1} \right)^{x}}}$Accordingly, in the example of FIG. 3A,

${{PDSV}\left( {efm}_{1} \right)} = {{\sum\limits_{x = 1}^{4}{{GZ}_{x} \cdot \left( {- 1} \right)^{x}}} = {{\left( {- 1} \right) + (2) + \left( {- 3} \right) + (5)} = 3}}$PDSV(m₂) = 2 PDSV(efm₂) = (4) + (−8) = −4 PDSV(m₃) = (−1) + (1) = 0PDSV(efm₃) = (−1) + (3) + (−8) = −6ZDSV(SEGMENT)

ZDSV(SEGMENT) is similar to PDSV except that the number of 0 groups iscounted from the start of the bit stream. It is formulated as follows:

${ZDSV} = {\sum\limits_{x = m}^{p}{{GZ}_{x} \cdot \left( {- 1} \right)^{x}}}$where

-   -   m represents the total number of 0 groups between the start of        the bit stream and the start of the segment.        Accordingly, in the example of FIG. 3A,

${{ZDSV}\left( {efm}_{1} \right)} = {{\sum\limits_{x = 1}^{4}{{GZ}_{x} \cdot \left( {- 1} \right)^{x}}} = {{\left( {- 1} \right) + (2) + \left( {- 3} \right) + (5)} = 3}}$${{ZDSV}\left( m_{2} \right)} = {{\sum\limits_{x = 5}^{5}{{GZ}_{x} \cdot \left( {- 1} \right)^{x}}} = {- 2}}$${{ZDSV}\left( {efm}_{2} \right)} = {{\sum\limits_{x = 6}^{7}{{GZ}_{x} \cdot \left( {- 1} \right)^{x}}} = {{(4) + \left( {- 8} \right)} = {- 4}}}$${{ZDSV}\left( m_{3} \right)} = {{\sum\limits_{x = 7}^{8}{{GZ}_{x} \cdot \left( {- 1} \right)^{x}}} = {{\left( {- 1} \right) + (1)} = 0}}$${{ZDSV}\left( {efm}_{3} \right)} = {{\sum\limits_{x = 8}^{10}{{GZ}_{x} \cdot \left( {- 1} \right)^{x}}} = {{(1) + \left( {- 3} \right) + (8)} = 6}}$ODD(SEGMENT)

ODD(SEGMENT) is used to indicate whether SEGMENT contains an odd-numberor an even-number of is, where SEGMENT is a series of consecutive bits.Each consecutive bit can be a channel-bit symbol, a merge-bit symbol, ora segment of bits starting at to and ending at a channel-bit symbol or amerge-bit symbol. If the number is odd, ODD(SEGMENT)=1; otherwise, ifthe number is even, ODD(SEGMENT)=0. In the example of FIG. 3A,

ODD(efm₁)=1; (three 1s)

ODD(m₂)=1; (one 1)

ODD(efm₂)=0; (two 1s)

ODD(m₃)=1; (one 1)

ODD(efm₃)=0; (two 1s)

ODD(t₀˜efm₁)=ODD(efm₁)=1; (three 1s)

ODD(t₀˜m₂)=0; (four 1s)

ODD(t₀˜efm₂)=0; (six 1s)

ODD(t₀˜efm₃)=0; (seven 1s)

ODD(t₀˜efm₂)=1; (nine 1s)

For ODD(t₀˜m₂), ODD(t₀˜efm₂), ODD(t₀˜m₃), ODD(t₀˜efm₂), they can beformulated as follows:

$\begin{matrix}{{{ODD}\left( {\left. t_{0} \right.\sim m_{2}} \right)} = {{{ODD}\left( {efm}_{1} \right)} \oplus {{ODD}\left( m_{2} \right)}}} \\{= {1 \oplus {1\mspace{14mu}\left( {{where} \oplus {{represents}\mspace{14mu}{the}\mspace{14mu}{XOR}\mspace{14mu}{logic}}} \right.}}} \\\left. {operation} \right) \\{= 0} \\{{{ODD}\left( {\left. t_{0} \right.\sim{efm}_{2}} \right)} = {{{ODD}\left( {\left. t_{0} \right.\sim m_{2}} \right)} \oplus {{ODD}\left( {efm}_{2} \right)}}} \\{= {0 \oplus 0}} \\{= 0} \\{{{ODD}\left( {\left. t_{0} \right.\sim m_{3}} \right)} = {{{ODD}\left( {\left. t_{0} \right.\sim{efm}_{2}} \right)} \oplus {{ODD}\left( m_{3} \right)}}} \\{= {0 \oplus 1}} \\{= 1} \\{{{ODD}\left( {\left. t_{0} \right.\sim{efm}_{3}} \right)} = {{{ODD}\left( {\left. t_{0} \right.\sim m_{3}} \right)} \oplus {{ODD}\left( {efm}_{3} \right)}}} \\{= {1 \oplus 0}} \\{= 1}\end{matrix}$

FIG. 4 is a schematic diagram used to depict the algorithm used tocompute ZDSV. Assume that SYM_(n) represents the original (n)th symbol.Through EFM, the (n−1)th channel-bit symbol efm_(n−1) is obtained fromthe (n−1)th symbol SYM_(n−1), and the (n)th channel-bit symbol efm_(n)is obtained from the (n)th symbol SYM_(n). Assume that m_(n) is themerge-bit symbol inserted between efm_(n−1) and efm_(n).

The values of ZDSV_(n−1), ODD(t₀˜efm_(n−1)), PDSV(m_(n)), ODD(m_(n)),DSV(efm_(n)), and ODD(efm_(n)) can be determined through the use of theabove-mentioned equations. Further, it can be deduced that:

ZDSV(m_(n)) = PDSV(m_(n)) * (−1)^(ODD(t0 − efm_(n − 1)))ODD(t₀ ∼ m_(n)) = ODD(t₀ ∼ efm_(n − 1)) ⊕ ODD(m_(n))ZDSV(efm_(n)) = PDSV(efm_(n)) * (−1)^(ODD(t0 − m_(n))) $\begin{matrix}{{{ODD}\left( {t_{0} \sim {efm}_{n}} \right)} = {{{ODD}\left( {t_{0} \sim m_{n}} \right)} \oplus {{ODD}\left( {efm}_{n} \right)}}} \\{= {{{ODD}\left( {t_{0} \sim {efm}_{n - 1}} \right)} \oplus {{ODD}\left( m_{n} \right)} \oplus {{ODD}\left( {efm}_{n} \right)}}}\end{matrix}$Accordingly, ZDSV_(n) can be formulated as follows:

$\begin{matrix}{{ZDSV}_{n} = {{ZDSV}_{n - 1} + {{ZDSV}\left( m_{n} \right)} + {{ZDSV}\left( {efm}_{n} \right)}}} \\{= {{ZDSV}_{n - 1} + {{{PDSV}\left( m_{n} \right)}*\left( {- 1} \right)^{{ODD}{({{t0} - {efm}_{n - 1}})}}} +}} \\{{{PDSV}\left( {efm}_{n} \right)}*\left( {- 1} \right)^{{ODD}{({{t0} - m_{n}})}}}\end{matrix}$Therefore,DSV _(n) =ZDSV _(n) +ODD(t ₀ ˜efm _(n))This equation shows that when ODD=1, i.e., the segment (t₀˜efm_(n))contains an odd-number of 1s, DSV=ZDSV+1; and when ODD=0, i.e., thesegment contains an even-number of 1s, DSV=ZDSV.

FIG. 5 is a schematic diagram used to show a comparison between DSV andZDSV when the starting logic voltage state of the NRZI signal is HIGHand the total number of 1s is an odd number.

As shown, it can be seen that, at the start, the ZDSV value is 0.Subsequently, since the first 0 is at the HIGH state, the ZDSV valuebecomes +1; subsequently, since the next three bits 100 are at the LOWstate and include two 0s, the ZDSV value becomes −1; subsequently, sincethe next four bits 1000 are at the HIGH state and include three 0s, theZDSV value becomes +2; and subsequently, since the next six bits 100000are at the LOW state, the ZDSV value becomes −3 at t₁.

Next, at the time point t₂, the ZDSV value becomes −1; subsequently att₃, the ZDSV value becomes +3; subsequently at t₄, the ZDSV valuebecomes +3; and finally at t₅, the ZDSV value becomes −3.

By contrast, the DSV value varies in such a manner that, at t₁, the DSVvalue is −4; at t₂, the DSV value becomes −1; at t₃, the DSV valuebecomes +3; at t₄, the DSV value becomes +2; and at t₅, the DSV valuebecomes −4.

Therefore, it can be learned that, in foregoing case, the NRZI signalvaries in voltage state for an odd-number of times, and the differencebetween the ZDSV value and the DSV value is 1, i.e., DSV=ZDSV −1;whereas when the total number of 1s is an even number, the NRZI signalvaries in voltage state for an even-number of times, and the differencebetween the ZDSV value and the DSV value is 0, i.e., ZDSV=DSV.

In the forgoing case, the computation for ZDSV and the conversion ofZDSV into DSV are disclosed in the following. The algorithm involves theuse of the following variables: GZ_(n), ZDSV, PDSV(SEGMENT),ZDSV(SEGMENT), and ODD(SEGMENT), which are introduced in the following.

GZ_(n)

Assume that, in a bit stream, each series of consecutive 0s arecollected as a group, with 1 serving as the separator between eachneighboring pair of 0 groups. Furthermore, assume that GZ_(n) representsthe total number of 0s in the (n)th 0 group. In the example of FIG. 5,starting at t₀, it can be easily seen that GZ₁=1, GZ₂=2, GZ₃=3, GZ₄=5,and so forth.

ZDSV

In this case, ZDSV can be formulated as follows:

${ZDSV} = {\sum\limits_{x = 1}^{n}{{GZ}_{x} \cdot \left( {- 1} \right)^{x + 1}}}$Here, the power of (−1) is x+1 instead of x because the start of theNRZI signal is positive. Accordingly, in the example of FIG. 5, at t₅,the ZDSV value is as follows:

$\begin{matrix}{{ZDSV} = {(1) + \left( {- 2} \right) + (3) + \left( {- 5} \right) + (2) + \left( {- 4} \right) + (9) + \left( {- 2} \right) + (3) + \left( {- 8} \right)}} \\{= {- 3}}\end{matrix}$PDSV(SEGMENT)

PDSV(SEGMENT) refers to Partial ZDSV of a particular segment in the bitstream, where the segment can be one of the 14-bit channel-bit symbolefm₁, efm₂, efm₃, or one of the 3-bit merge-bit symbols m₂, m₃. PDSV canbe formulated as follows:

${PDSV} = {\sum\limits_{x = 1}^{n}\;{{GZ}_{x} \cdot \left( {- 1} \right)^{x + 1}}}$Accordingly, in the example of FIG. 5,

$\begin{matrix}{{{PDSV}\left( {efm}_{1} \right)} = {{\sum\limits_{x = 1}^{4}\;{{GZ}_{x} \cdot \left( {- 1} \right)^{x + 1}}} = {{(1) + \left( {- 2} \right) + (3) + \left( {- 5} \right)} = {- 3}}}} \\{{{PDSV}\left( m_{2} \right)} = {- 2}} \\{{{PDSV}\left( {efm}_{2} \right)} = {{\left( {- 4} \right) + (8)} = 4}} \\{{{PDSV}\left( m_{3} \right)} = {{(1) + \left( {- 1} \right)} = 0}} \\{{{PDSV}\left( {efm}_{3} \right)} = {{(1) + \left( {- 3} \right) + (8)} = 6}}\end{matrix}$ZDSV(SEGMENT)

ZDSV(SEGMENT) is similar to PDSV except that the number of 0 groups iscounted from the start of the bit stream. It is here formulated asfollows:

${ZDSV} = {\sum\limits_{x = m}^{p}\;{{GZ}_{x} \cdot \left( {- 1} \right)^{x + 1}}}$where

-   -   m represents the total number of 0 groups between the start of        the bit stream and the start of the segment.        Accordingly, in the example of FIG. 5,

$\begin{matrix}{{{ZDSV}\left( {efm}_{1} \right)} = {{\sum\limits_{x = 1}^{4}\;{{GZ}_{x} \cdot \left( {- 1} \right)^{x + 1}}} = {{(1) + \left( {- 2} \right) + (3) + \left( {- 5} \right)} = {- 3}}}} \\{{{ZDSV}\left( m_{2} \right)} = {{\sum\limits_{x = 5}^{5}\;{{GZ}_{x} \cdot \left( {- 1} \right)^{x + 1}}} = 2}} \\{{{ZDSV}\left( {efm}_{2} \right)} = {{\sum\limits_{x = 6}^{7}\;{{GZ}_{x} \cdot \left( {- 1} \right)^{x + 1}}} = {{\left( {- 4} \right) + (8)} = 4}}} \\{{{ZDSV}\left( m_{3} \right)} = {{\sum\limits_{x = 7}^{8}\;{{GZ}_{x} \cdot \left( {- 1} \right)^{x + 1}}} = {{(1) + \left( {- 1} \right)} = 0}}} \\{{{ZDSV}\left( {efm}_{3} \right)} = {{\sum\limits_{x = 8}^{10}\;{{GZ}_{x} \cdot \left( {- 1} \right)^{x + 1}}} = {{\left( {- 1} \right) + (3) + \left( {- 8} \right)} = {- 6}}}}\end{matrix}$ODD(SEGMENT)

ODD(SEGMENT) is used to indicate whether SEGMENT contains an odd-numberor an even-number of 1s. If the number is odd, ODD(SEGMENT)=1;otherwise, if the number is even, ODD(SEGMENT)=0.

Assume that SYM_(n) represents the original (n)th symbol. Through EFM,the (n−1)th channel-bit symbol efm_(n−1) is obtained from the (n−1)thsymbol SYM_(n−1), and the (n)th channel-bit symbol efm_(n) is obtainedfrom the (n)th symbol SYM_(n). Assume that m_(n) is the merge-bit symbolinserted between efm_(n−1) and efm_(n).

The values of ZDSV_(n−1), ODD(t₀˜efm_(n−1)), PDSV(m_(n)), ODD(m_(n)),DSV(efm_(n)), and ODD(efm_(n)) can be determined through the use of theabove-mentioned equations. Further, it can be deduced that:

$\begin{matrix}{{{ZDSV}\left( m_{n} \right)} = \;{{{PDSV}\left( m_{n} \right)}*\left( {- 1} \right)^{{ODD}{({t_{0} - {efm}_{n - 1}})}}}} \\{{{ODD}\left( {t_{0} \sim m_{n}} \right)} = {{{ODD}\left( {t_{0} \sim {efm}_{n - 1}} \right)} \oplus {{ODD}\left( m_{n} \right)}}} \\{{{ZDSV}\left( {efm}_{n} \right)} = {{{PDSV}\left( {efm}_{n} \right)}*\left( {- 1} \right)^{{ODD}{({t_{0} - m_{n}})}}}} \\{{{ODD}\left( {t_{0} \sim {efm}_{n}} \right)} = {{{ODD}\;\left( {t_{0} \sim m_{n}} \right)} \oplus {{ODD}\left( {efm}_{n} \right)}}} \\{= {{{ODD}\;\left( {t_{0} \sim {efm}_{n - 1}} \right)} \oplus {{ODD}\left( m_{n} \right)} \oplus {{ODD}\left( {efm}_{n} \right)}}}\end{matrix}$Accordingly, ZDSV_(n) can be formulated as follows:

$\begin{matrix}{{ZDSV}_{n} = \;{{ZDSV}_{n - 1} + {{ZDSV}\left( m_{n} \right)} + {{ZDSV}\left( {efm}_{n} \right)}}} \\{= \begin{matrix}{{ZDSV}_{n - 1} + {{{PDSV}\left( m_{n} \right)}*\left( {- 1} \right)^{{ODD}{({t_{0} - {efm}_{n - 1}})}}} +} \\{{{{PDSV}\left( {efm}_{n} \right)}*\left( {- 1} \right)^{{ODD}{({t_{0} - m_{n}})}}}\mspace{166mu}}\end{matrix}}\end{matrix}$Therefore,DSV _(n) =ZDSV _(n) −ODD(t ₀ ˜efm _(n))This equation shows that when ODD=1 (i.e., the segment contains anodd-number of 1s), DSV=ZDSV −1; and when ODD=0 (i.e., the segmentcontains an even-number of 1s), DSV=ZDSV.Implementation of the Invention

FIG. 6 is a schematic block diagram showing the system architecture ofthe DSV computation method and system according to the invention. Asshown, the system architecture includes an EFM processing unit 100, aPDSV processing unit 110, an ODD checking circuit 120, a run-lengthchecking circuit 130, a first buffer 150, a second buffer 200, a thirdbuffer 190, an inhibit circuit 160, a search circuit 170, a firstmultiplexer 220, a second multiplexer 180, an arithmetic unit 210, and aDSV computation circuit 300. The EFM processing unit 100 and the PDSVprocessing unit 110 are two separate memory units which are used toimplement a lookup table that allows each input 8-bit symbol SYM_(n) tofind its corresponding channel-bit symbol efm_(n) and PDSV(efm_(n)).

The efm_(n) data is outputted from the EFM processing unit 100 and thentransferred to both the ODD checking circuit 120 and the run-lengthchecking circuit 130, while the PDSV(efm_(n)) data is outputted from thePDSV processing unit 110 and then transferred to the DSV computationcircuit 300. The merge-bit selection signal m_(n—)SEL varies statesequentially in such a manner as to represent the selection of one ofthe four merge-bit symbols m₀=(000), m₁=(001), m₂=(010), and m₃=(100).These four merge-bit symbols are then inserted one by one betweenefm_(n) and efm_(n−1) to compute the corresponding DSV_(n) values, whichare respectively denoted by DSV_(n)(m₀), DSV_(n)(m₁), DSV_(n)(m₂), andDSV_(n)(m₃).

The run-length checking circuit 130 is used to check whether the currentchannel-bit symbol efm_(n), after one merge-bit symbol has beeninserted, will be compliant with the specified run length. To do this,the run-length checking circuit 130 first checks the 0 groups of the 14bits of emf_(n) and thereby assigns the first 0 group GZ₁ as LRUN_(n)and the last 0 group GZ_(LAST) as RRUN_(n). In the example ofemf_(n)=(01001000100000), GZ₁=1 so that LRUN_(n)=1, and GZ_(LAST)=5 sothat RRUN_(n)=5. The first buffer 150 is used for temporary storage ofthe RRUN_(n) value of the previous channel-bit symbol efm_(n−1). Therun-length checking circuit 130 then sends the RRUN_(n) value to thefirst buffer 150 to replace the RRUN_(n−1) value previously storedtherein, and meanwhile sends the LRUN_(n) value to the inhibit circuit160.

Under control of the m_(n—)SEL signal, the inhibit circuit 160 firstreads the LRUN_(n) value and the RRUN_(n−1) value, respectively, fromthe run-length checking circuit 130 and the first buffer 150, thensuccessively inserts each of the four merge-bit symbols m₀=(000),m₁=(001), m₂=(010), and m₃=(100) between the RRUN_(n−1) and the LRUN_(n)value, and then checks whether the combined bit stream is compliant withthe run length or not. If not compliant, the corresponding merge-bitsymbol (hereinafter referred to as an invalid merge-bit symbol) will besent via the INHIBIT0˜3 data line to the search circuit 170, allowingthe search circuit 170 to eliminate the DSV_(n) corresponding to theinvalid merge-bit symbol. For instance, if m₁ is an invalid merge-bitsymbol, then DSV₁(m₁) is eliminated.

The DSV computation circuit 300 is designed to compute DSV_(n)(m₀),DSV_(n)(m₁), DSV_(n)(m₂), and DSV_(n)(m₃) in accordance with theabove-mentioned equations.

The ODD checking circuit 120 is used to perform the following steps: afirst step of receiving efm_(n) from the EFM processing unit 100 andODD(t₀˜efm_(n−1)) from the third buffer 190; a second step ofdetermining ODD(efm_(n)); a third step of determining ODD(m_(n)) undercontrol of the m_(n—)SEL signal; and a final step of determiningODD(t₀˜efm_(n))=ODD(t₀˜efm_(n−1))⊕ODD(m_(n))⊕ODD(efm_(n)) for m₀, m₁,m₂, and m₃, respectively. The resulting four pieces of data are thentransferred to the DSV computation circuit 300 for further processing.

The DSV computation circuit 300 receives the PDSV(efm_(n)) data from thePDSV processing unit 110, the ODD(t₀˜efm_(n)) data from the ODD checkingcircuit 120, the ODD(t₀˜efm_(n−1)) data from the third buffer 190, andthe ZDSV_(n−1) data from the second buffer 200, and then computes forDSV_(n)(m₀) at the appearance of the m_(n—)SEL signal for m₀ inaccordance with the following equations:

$\mspace{85mu}\begin{matrix}{{ZDSV}_{n} = \;{{ZDSV}_{n - 1} + {{ZDSV}\left( m_{n} \right)} + {{ZDSV}\left( {efm}_{n} \right)}}} \\{= \begin{matrix}{{ZDSV}_{n - 1} + {{{PDSV}\left( m_{n} \right)}*\left( {- 1} \right)^{{ODD}{({t_{0} - {efm}_{n - 1}})}}} +} \\{{{{PDSV}\left( {efm}_{n} \right)}*\left( {- 1} \right)^{{ODD}{({t_{0} - m_{n}})}}}\mspace{166mu}}\end{matrix}}\end{matrix}$  ODD (t₀ ∼ m_(n)) = ODD (t₀ ∼ efm_(n − 1)) ⊕ ODD (m_(n))       DSV_(n) = ZDSV_(n) + ODD (t₀ ∼ efm_(n))The DSV_(n)(m₀) data is then transferred both to the search circuit 170and to the first multiplexer 220 and latched thereby. Meanwhile, theODD(t₀˜efm_(n)) data for m₀, denoted as ODD(t₀˜efm_(n))m₀, istransferred back to the second multiplexer 180.

In a similar manner, DSV_(n)(m₁), DSV_(n)(m₂), and DSV_(n)(m₃) can bedetermined, and are then transferred both to the search circuit 170 andto the first multiplexer 220. Meanwhile, ODD(t₀˜efm_(n))m₁,ODD(t₀˜efm_(n))m₂, and ODD(t₀˜efm_(n))m₃ are transferred to the secondmultiplexer 180 to be latched therein.

The search circuit 170, based on the information about the invalidmerge-bit symbol from the INHIBIT0˜3 data line, first eliminates any oneof the DSV_(n)(m₀), DSV_(n)(m₁), DSV_(n)(m₂), DSV_(n)(m₃) correspondingto the invalid merge-bit symbol, and then, from the remaining ones,chooses the one whose value is closest to zero (i.e., the one whoseabsolute value is minimum). The corresponding merge-bit symbol of thechosen DSV_(n), referred to as the optimal merge-bit symbol, is thenindicated via the m_(n—)Index data line to the second multiplexer 180and the first multiplexer 220. The m_(n—)Index signal causes the secondmultiplexer 180 to select the ODD(t₀˜efm_(n)) corresponding to theoptimal merge-bit symbol and then transfers the selected one to thethird buffer 190 and the arithmetic unit 210. Meanwhile, the m_(n—)Indexsignal causes the first multiplexer 220 to select the DSV_(n)corresponding to the optimal merge-bit symbol and then transfer theselected one to the arithmetic unit 210. At the arithmetic unit 210, thefollowing arithmetic operation is performed to obtain ZDSV_(n):ZDSV _(n) =DSV _(n) −ODD(t ₀ ˜efm _(n))Note that in the foregoing case, the arithmetic unit 210 performs asummation operation, but when the starting logic voltage state of theNRZI signal is HIGH, the above arithmetic operation will beZDSV_(n)=DSV_(n)+ODD(t₀˜efm_(n)), and thus the arithmetic unit 210performs a subtraction operation. The obtained ZDSV_(n) is thentransferred to the second buffer 200. Next, the current ZDSV_(n) andODD(t₀˜efm_(n)) data stored respectively in the second buffer 200 andthe third buffer 190 are fetched as ZDSV_(n−1) and ODD(t₀˜efm_(n−1)) forthe next symbol SYM_(n) to find its optimal merge-bit symbol.

FIG. 7 is a schematic diagram showing the inside circuit architecture ofthe ODD checking circuit 120 used in the DSV computation system of theinvention shown in FIG. 6. As shown, the ODD checking circuit 120includes a multiplexer 122, a first XOR gate 124, a second XOR gate 126,and a third XOR gate 128. When the m_(n—)SEL signal represents m₀, itcauses the multiplexer 122 to select ODD(m₀) as output. The first XORgate 124 processes efm_(n) to obtain ODD(efm_(n)). The second XOR gate126 and the third XOR gate 128 in combination perform following thelogic operation to obtain ODD(t₀˜efm_(n)):ODD(t₀ ˜efm _(n))=ODD(t₀ ˜efm _(n−1))⊕ODD(m _(n))⊕ODD(efm _(n))Since the output ODD(t₀˜efm_(n)) corresponds to m₀, it is denoted asODD(t₀˜efm_(n))m₀.

In a similar manner, when the m_(n—)SEL signal successively representsm₁, m₂, and m₃, the output ODD(t₀˜efm_(n))m₁, ODD(t₀˜efm_(n))m₂, andODD(t₀˜efm_(n))m₃ will be successively obtained.

FIG. 8 is a schematic diagram showing the inside circuit architecture ofthe DSV computation circuit 300 used in the DSV computation system ofthe invention shown in FIG. 6. As shown, the DSV computation circuit 300includes a first multiplexer 310, a second multiplexer 320, a first XORgate 330, a second XOR gate 340, a third XOR gate 350, an adder 360, aC-adder (add with carry) 370, a first buffer 380, a second buffer 381, athird buffer 382, and a fourth buffer 383. When the m_(n—)SEL signalrepresents m₀, it causes the first multiplexer 310 to select PDSV(m₀) asoutput and meanwhile causes the second multiplexer 320 to select ODD(m₀)as output. The first XOR gate 330 then performs the logic operationPDSV(m₀)⊕ODD(t₀˜efm_(n−1)) to obtain the output ZDSV(m_(n)). Meanwhile,the second XOR gate 340 performs the logic operation ODD(m₀)⊕ODD(t₀˜efm_(n−1)) to obtain the output ODD(t₀˜m_(n)). Subsequently,the third XOR gate 350 performs the logic operationODD(t₀˜m_(n))⊕PDSV(efm_(n)) to obtain the output ZDSV(efm_(n)). Afterthis, the adder 360 performs the arithmetic operationZDSV(m_(n))+ZDSV(efm_(n)), and subsequently, the second buffer 381 addsZDSV_(n−1) to the output of the adder 360 with ODD(t₀˜efm_(n)) from theODD checking circuit 120 (FIG. 6) being used as carry bit. The output ofthe C-adder 370 serves as the desired DSV_(n)(m₀), which is thentransferred to the first buffer 380. The ODD(t₀˜efm_(n))m₀ data isstored together with the DSV_(n)(m₀) data in the first buffer 380.

Subsequently, the m_(n—)SEL signal changes states to represent m₁, m₂,and m₃ in a sequential manner to cause the DSV computation circuit 300to successively produce DSV_(n)(m₁), DSV_(n)(m₂), and DSV_(n)(m₃). TheDSV_(n)(m₁) and ODD(t₀˜efm_(n))m₁ data are stored together in the secondbuffer 381; the DSV_(n)(m₂) and ODD(t₀˜efm_(n))m₂ data are storedtogether in the third buffer 382; and the DSV_(n)(m₃) andODD(t₀˜efm_(n))m₃ data are stored together in the fourth buffer 383.

The invention is also applicable for use with a DVD system in whichdigitized video data are also represented by 8-bit symbols and convertedthrough EFM into 14-bit channel-bit symbols. The difference is that inthe DVD system, the EFM produces a number of 14-bit channel-bit symbolscorresponding to each original 8-bit symbol. For this reason, there isno need to find the optimal merge-bit symbol and it is only required tofind any one of the channel-bit symbols that is compliant with the runlength.

FIG. 9 is a schematic diagram used to depict how to compute for ZDSV ina DVD system. In this case, assume that one channel-bit symbol efm_(n−1)is obtained by processing the (n−1)th symbol SYM_(n−1) through EFM, anda number of channel-bit symbols efm_(n—) _(i) are obtained by processingthe (n)th symbol SYM_(n) through EFM.

In this case, the values of ZDSV_(n−1), ODD(t₀˜efm_(n−1)),PDSV(efm_(n—i)), and ODD(efm_(n—i)) for efm_(n—i) can be determinedthrough the use of the above-mentioned equations. It can be deducedthat:ZDSV(efm _(n—i))=PDSV(efm _(n—i))*(−1)^(OOD(t0−efm) ^(n−1) )ODD(t ₀ ˜efm _(n—i))=ODD(t ₀ ˜efm _(n−1))⊕ODD(efm _(n—i))Accordingly, ZDSV_(n−1) can be formulated as follows:

$\begin{matrix}{{ZDSV}_{n\_ i} = \;{{ZDSV}_{n - 1} + {{ZDSV}\left( {efm}_{n\_ i} \right)}}} \\{= {{ZDSV}_{n - 1} + {{{PDSV}\left( {efm}_{n\_ i} \right)}*\left( {- 1} \right)^{{ODD}{({t_{0} - {efm}_{n - 1}})}}}}}\end{matrix}$Therefore,DSV _(n—i) =ZDSV _(n−1) +ODD(t ₀ ˜efm _(n—i))

Next, all the efm_(n—i) corresponding to SYM_(n) are plugged into theabove equation to obtain a number of DSV_(n—) _(i) values, and fromwhich the efm_(n—i) corresponding to the DSV_(n—i) having the minimumabsolute value is chosen as the optimal channel-bit symbol for SYM_(n).

In conclusion, the invention provides a DSV computation method andsystem which is capable of determining the DSV value of a bit stream tofind the optimal merge-bit symbol for insertion between each succeedingpair of channel-bit symbols. Compared to the prior art, the inventioncan find the optimal merge-bit symbol based on DSV in a morecost-effective manner with a reduced amount of memory and utilizes alookup table requiring a reduced amount of memory space for storage sothat memory space can be reduced as compared to the prior art. Theinvention is therefore more advantageous to use than the prior art.

The invention has been described using exemplary preferred embodiments.However, it is to be understood that the scope of the invention is notlimited to the disclosed embodiments. On the contrary, it is intended tocover various modifications and similar arrangements. The scope of theclaims, therefore, should be accorded the broadest interpretation so asto encompass all such modifications and similar arrangements.

1. A method for computing a zero digital sum variation (ZDSV) of astream of channel-bit symbols, comprising the steps of: (a) providing aninitial value ZDSV_(n−1), an initial value ODD(t₀˜efm_(n−1)) and ainitial bias value, wherein the initial value ZDSV_(n−1) is the zerodigital sum variation of a previous start-to-channel-bit symbolefm_(n−1), wherein the ODD(t₀˜efm_(n−1)) indicates that the stream ofthe channel-bit symbols from a starting logic voltage state to theprevious start-to-channel-bit symbol efm_(n−1) contains an odd-number oran even-number of 1s, the initial bias value is either 1 or −1; (b)providing a current channel-bit symbol efm_(n), and obtaining a partialdigital sum variation (PDSV) value PDSV(efm_(n)) and a ODD(efm_(n))value in accordance with the current symbol efm_(n); (c) obtaining aplurality of partial digital sum variation (PDSV) values PDSV(m_(n)^(i)) and ODD(m_(n) ^(i)) values in accordance with all possiblemerge-bit symbols m_(n) ^(i), wherein i=0, 1, . . . , x, the number ofthe possible merge-bit symbols is x+1; (d) calculating ZDSV_(n)^(i)=ZDSV_(n−1)+ZDSV(m_(n) ^(i))+ZDSV(efm_(n))_(i) and calculating andODD(t₀˜efm_(n))_(i)=ODD(t₀˜efm_(n−1))⊕ODD(m_(n) ^(i))⊕ODD(efm_(n)),wherein i=0, 1, . . . , x, in order to determine the ZDSV_(n) of thezero digital sum variation of the current channel-bit symbol efm_(n),wherein ZDSV(m_(n) ^(i))=PDSV(m_(n) ^(i))*(−1)^(ODD(t) ⁰ ^(˜efm) ^(n−1)⁾ and ZDSV(efm_(n))_(i)=PDSV(efm_(n))*(−1)^(ODD(t) ⁰ ^(˜m) ^(n) ^(i) ⁾,wherein ODD(t₀˜m_(n) ^(i))=ODD(t₀˜efm_(n−1))⊕ODD(m_(n) ^(i)), wherein⊕represents the XOR logic operation, the ZDSV_(n) ^(i) is the zerodigital sum variation of the channel-bit symbol efm_(n) corresponding tothe i-th merge-bit symbol of the possible merge-bit symbols, theZDSV(m_(n) ^(i)) means a zero digital sum variation of the i-thmerge-bit symbol of the possible merge-bit symbols corresponding to thecurrent channel-bit symbol efm_(n), the ZDSV(efm_(n))_(i) means a zerodigital sum variation of the current channel-bit symbol efm_(n)corresponding to the i-th merge-bit symbol of the possible merge-bitsymbols; (e) DSV_(n) ^(i)=ZDSV_(n) ^(i)+(initial biasvalue)*ODD(t₀˜efm_(n−1))_(i), wherein the DSV_(n) ^(i) is a digital sumvariation of the current channel-bit symbol efm_(n) corresponding to thei-th merge-bit symbol of the possible merge-bit symbols; (f) determininga final merge-bit symbol m_(n) ^(j) in accordance with the absolutevalue of DSV_(n) ^(i) and a run time limit, wherein jε{i}, wherein i=0,1, . . . , x; and (f) assigning the initial value ZDSV_(n−1)=ZDSV_(n)^(j), the ODD(t₀˜efm_(n−1))=ODD(t₀˜efm_(n))_(j), and then jumping tostep (b).
 2. A method for use on a DVD system for computing a digitalsum variation (DSV) of a data stream, comprising the steps of: (a)providing a pre-determined zero digital sum variation initial valueZDSV_(n−1), an initial value ODD(t₀˜efm_(n−1)) and an initial biasvalue, the initial bias value is either 1 or −1; (b) converting the datastream into a plurality of channel-bit symbol efm_(n) ^(i), wherein i=0,1, 2, . . . , x; (c) obtaining a partial digital sum variation (PDSV)value PDSV(efm_(n) ^(i)) and a ODD(efm_(n) ^(i)) value in accordancewith the channel-bit symbol efm_(n) ^(i), wherein i=0, 1, 2, . . . , x;(d) calculating ZDSV_(n) ^(i)=ZDSV_(n−1)+ZDSV(efm_(n) ^(i)) andODD(t₀˜efm_(n) ^(i))=ODD(t₀˜efm_(n−1)) ⊕ODD(efm_(n) ^(i)), wherein i=0,1, . . . , x, in order to determine the ZDSV_(n) ^(i) of the zerodigital sum variation of the current channel-bit symbol efm_(n) ^(i),wherein ZDSV(efm_(n) ^(i))=PDSV(efm_(n) ^(i))* (−1)^(ODD(t) ⁰ ^(−efm)^(n−1) ⁾, wherein the ZDSV_(n) ^(i) is the zero digital sum variation ofthe i-th channel-bit symbol efm_(n) ^(i), the ZDSV(efm_(n) ^(i)) means azero digital sum variation of the i-th channel-bit symbol efm_(n) ^(i);(e) DSV_(n) ^(i)=ZDSV_(n) ^(i)+(the initial bias value)*ODD(t₀˜efm_(n)^(i)), wherein the DSV_(n) ^(i) is a digital sum variation of the i-thchannel-bit symbol efm_(n) ^(i); (f) determining a final merge-bitsymbol efm_(n) ^(j) in accordance with the absolute value of the DSV_(n)^(i) and a coding rule, wherein jε{i}, wherein i=0, 1, . . . , x; and(f) assigning the initial value ZDSV_(n−1)=ZDSV_(n) ^(j), theODD(t₀˜efm_(n−1))=ODD(t₀˜efm_(n) ^(j)), and then jumping to step (b). 3.A method for use on a DVD system for computing a digital sum variation(DSV) of a data stream, comprising the steps of: (a) providing apre-determined zero digital sum variation initial value ZDSV_(n−1) andan initial value ODD(t₀˜efm_(n−1)); (b) converting the data stream intoa plurality of channel-bit symbol efm_(n) ^(i), wherein i=0, 1, 2, . . ., x; (c) obtaining a partial digital sum variation (PDSV) valuePDSV(efm_(n) ^(i)) and a ODD(efm_(n) ^(i)) value in accordance with thecorresponding channel-bit symbol efm_(n) ^(i), wherein i=0, 1, 2, . . ., x; (d) calculating ZDSV_(n) ^(i)=ZDSV_(n−1)+ZDSV(efm_(n) ^(i)) andODD(t₀˜efm_(n) ^(i))=ODD(t₀˜efm_(n−1)) ⊕ODD(efm_(n) ^(i)), wherein i=0,1, . . . , x, in order to determine the ZDSV_(n) ^(i)of the zero digitalsum variation of the current channel-bit symbol efm_(n) ^(i), whereinZDSV(efm_(n) ^(i))=PDSV(efm_(n) ^(i))* (−1^(ODD(t) ^(o) ^(˜efm) ^(n−1)⁾, wherein the ZDSV_(n) ^(i) is the zero digital sum variation of thei-th channel-bit symbol efm_(n) ^(i), the ZDSV(efm_(n))_(i) means a zerodigital sum variation of the i-th channel-bit symbol efm_(n) ^(i), (e)determining a final merge-bit symbol efm_(n) ^(j) in accordance with theabsolute value of the ZDSV(efm_(n) ^(i)) and a coding rule, whereinjε{i}, wherein i=0, 1, . . . , x; and (f) assigning the initial valueZDSV_(n−j)=ZDSV_(n) ^(j), the ODD(t₀˜efm_(n−1))=ODD(t₀˜efm _(n) ^(j)),and then jumping to step (b).